t1090p6 www.vishay.com vishay semiconductors rev. 1.0, 26-sep-14 1 document number: 84269 for technical questions, contact: optochipsupport@vishay.com this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 silicon npn phototransistor description t1090p6 is a silicon npn phototransistor chip with high radiant sensitivity, sensitive to visible and near infrared radiation. features ? package type: chip ? package form: single chip ? dimensions (l x w x h in mm): 0.52 x 0.52 x 0.185 ? high photo sensitivity ? radiant sensitive area: 0.14 mm 2 ? high radiant sensitivity ? suitable for visible and near infrared radiation ? fast response times ? material categorization: fo r definitions of compliance please see www.vishay.com/doc?99912 general information the datasheet is based on vishay optoel ectronics sample testing under certain predetermined and assumed conditions, and is provided for illustration purpose only. customers are encouraged to perform testing in actual proposed packaged and used conditions. vishay optoelectronics die products are tested us ing vishay optoelectronics base d quality assurance procedures and are manufactured using vishay optoelectronics established pr ocesses. estimates such as th ose described and set forth in this datasheet for semicond uctor die will vary de pending on a number of packaging, hand ling, use, and other factors. therefore sold die may not perform on an equivale nt basis to standard package products. note ? test condition see table basic characteristics note ? moq: minimum order quantity product summary component i ca (a) ? (deg) 0.5 (nm) t1090p6 65 to 750 60 620 to 1000 ordering information ordering code packaging remarks package form T1090P6-SD-F wafer sawn on foil wi th disco frame moq: 250 000 pcs chip absolute maximum ratings (t amb = 25 c, unless otherwise specified) parameter test condition symbol value unit collector emitter voltage v ceo 80 v emitter collector voltage v eco 7.8 v collector current i c 50 ma junction temperature t j 125 c operating temperature range t amb -55 to +125 c storage temperature range t stg1 -55 to +150 c storage temperature range on foil t stg2 -40 to +50 c
t1090p6 www.vishay.com vishay semiconductors rev. 1.0, 26-sep-14 2 document number: 84269 for technical questions, contact: optochipsupport@vishay.com this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 notes ? the measurements are based on samples of die which are mounted on a to18-header without resin coating (1) specific selection types possible basic characteristics (t amb = 25 c, unless otherwise specified) fig. 1 - relative spectral sensitivity vs. wavelength fig. 2 - turn-on time vs. load resistance fig. 3 - turn-off time vs. load resistance fig. 4 - collector emi tter capacitance vs. coll ector emitter voltage basic characteristics (t amb = 25 c, unless otherwise specified) parameter test condition symbol min. typ. max. unit collector emitter breakdown voltage i c = 10 a, e = 0 v (br)ceo 80 v collector emitter dark current v ce = 50 v, e = 0 i ceo 150na collector light current (vishay selection type (1) ) e e = 1 mw/cm 2 , = 950 nm, v ce = 5 v i ca 65 750 a wavelength of peak sensitivity p 840 nm range of spectral bandwidth 0.5 620 to 1000 nm rise time v ce = 5 v, i c = 2 ma, r l = 100 t r 4.3 s fall time v ce = 5 v, i c = 2 ma, r l = 100 t f 7.7 s 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 400 500 600 700 800 900 1000 1100 s ( ) rel - relative s pectral s en s itivity - wavelength (nm) 1 10 100 1000 10 000 t on ( s ) r l ( ) v ce = 5 v = 960 nm i ce = 10 ma for r l = 100 i ca group k2 1 10 100 1000 100 1000 10 000 t off ( s ) r l ( ) v ce = 5 v = 960 nm i ce = 10 ma for r l = 100 i ca group k2 0 1 2 3 4 5 6 7 8 9 0.1 1 10 100 c ceo - collector emitter capacitance (pf) v ce - collector emitter voltage (v) f = 1 mhz
t1090p6 www.vishay.com vishay semiconductors rev. 1.0, 26-sep-14 3 document number: 84269 for technical questions, contact: optochipsupport@vishay.com this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 dimensions in millimeters mechanical dimensions parameter symbol min. typ. max. unit length of chip edge (x-direction) l x 0.52 mm length of chip ed ge (y-direction) l y 0.52 mm sensitive area a s 0.14 mm 2 wafer diameter d 150 mm die height h 0.170 0.185 0.200 mm bond pad diameter emitter d 0.120 mm bond pad diameter base d 0.100 mm notes ? not indicated tolerance s : 0.005 (1) only for information: dimen s ion of s awn die under con s ideration of 30 m s aw kerf drawing-no.: 9.000-5078.3-4 i ss ue: 3; 03.05.2011 (0.52) (1) (0.52) (1) 0.4 0.4 technical drawing s according to din s pecification s orientation of wafer flat bonding area: e: ? 120 m b: ? 100 m opt. active area: 0.135 mm 2 b: ba s e thickne ss : 185 m 15 m bonding re s tricted to thi s area in order to avoid damage of adjacent s tructure s e: emitter ? 0.1 bond ing area ? 0.12 metallization ? 0.12 bonding area y 400:1 y b e b e
t1090p6 www.vishay.com vishay semiconductors rev. 1.0, 26-sep-14 4 document number: 84269 for technical questions, contact: optochipsupport@vishay.com this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 note ? all chips are checked in accordance with the vishay semiconductor, specification of visual inspection fvov6870. the visual inspection shall be made in accordance with the specification of visual inspection as referenced. the visual inspe ction of chip backside is performed wi th stereo microscope with incident light and 40x to 80x magnification. the quality inspection (final visual inspection) is performed by production. an addition al visual inspection step as special re lease procedure by qm is not installed. handling and storage conditions ? the hermetically sealed shipment lots shall be opened in temperature and moistu re controlled cleanroom environment only. it is mandatory to follow the rules for disposition of ma terial that can be hazardous for humans and environment. ? product must be handled only at esd safe workstations. standard esd precaution s and safe work environments are as defined in mil-hdbk-263. ? singulated die are not to be handled with tweezers. a vacuum wand with non metallic esd pro tected tip shou ld be used. packing chips are fixed on adhesive foil. upon re quest the foils can be mounted on plastic frame or disco frame. for shipment, the wafers are arranged to stacks and hermeti cally sealed in plastic bags to ensure protection against environmental influence (humidity and contamination). use for recycling reliable operator s only. we can help getting in touch with your nearest sales office. by agreement we will ta ke back packing material, if it is sorted. you will have to bear the costs of transport. we will invoice you for any costs incurre d for packing material that is returned unsorted or which we are not obliged to accept. additional information frontside metallization, base (b), emitter (e) alsi 1.2 m backside metallization, collector ausb 1.2 m dicing sawing die bonding technology epoxy bonding
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